25/10G ULTRA Low Latency FPGA IP Core Solution


The 25Gbps Ultra Low Latency Ethernet IP solution offers a fully integrated IEEE P802.3by compliant package for NIC (Network Interface Card) and Ethernet switching applications. This ultra-low latency solution specifically targeted for demanding financial, high frequency trading, HPC, and next generation 5G network applications.


  • Round Trip Latency of 59.6ns + Device Specific Transceiver Latency
  • As shown in the figure, the 25Gbps ULL Ethernet IP solution includes:
  • Ultra low latency MAC; Tx = 17.4ns , Rx = 17.4ns; (64-bit user interface mode)
  • Ultra low latency 25GBase-R PCS; Tx = 12.4ns, Rx = 12.4ns; (64-bit user interface mode)
  • Technology dependent transceiver wrapper (includes clock PLLs) for Altera and/or Xilinx FPGAs
  • Statistics counter block (for RMON and MIB)
  • MDIO and I2C cores for optical module status and control


  • Ethernet wrapper design with:
    • Top level MAC and PCS wrappers (source files, Verilog) for user specific customizations
    • Compiled synthesizable binaries (Netlists) for MAC and PCS cores
    • Compiled synthesizable binaries (Netlists) for L2 packet generator and checker
    • Technology specific transceiver wrappers for the selected device family
    • Source code RTL (Verilog) for RMON and Register-File blocks
  • UART/PCIe interface based reference design with:
    • Top level wrapper (source files, Verilog) for user specific customizations
    • Compiled synthesizable binaries (Netlists) for the I2C and MDIO cores
    • Compiled synthesizable binaries (Netlists) for the UART or PCIe host interface
  • Encrypted RTL for MAC, PCS and packet generator/checker for simulation
  • Constraint files and synthesis scripts for design compilation
  • PCIe driver/API (source files, C) for Linux with the optional PCIe host interface
  • GUI application (Linux only) for interfacing to the reference design
  • Design guide(s) and user manuals

Product Brief

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