Overview
The 200Gbps Ethernet FPGA IP core solution offers a fully integrated IEEE802.3bs compliant solution for use in core networks, Ethernet switching and network interface card (NIC) applications. The Ethernet cores implement an efficient architecture to achieve best in class resource utilization and performance numbers for targeting the complete 200Gbps Ethernet solution to ASICs as well as FPGAs.
Features
- 200GBase-R PCS core with RS-FEC(544,514) KP4
- 200Gbps MAC core with streaming user
- Technology dependent transceiver wrappers for NRZ/ PAM4 SERDES
- RMON block for statistics
- Synthesizable packet generator/checker for quick bring up and standalone verification of 200G Ethernet solution.
- AXI4-Lite or Avalon-MM based fabric for host interface register
- Linux based APIs/tools for configuration of the 200G Ethernet cores and getting various
- MDIO and I2C cores for optical module control and status.
Deliverables
- Encrypted MAC and PCS RTL for simulation and synthesis
- Encrypted L2 packet generator and checker RTL for simulation and synthesis
- Source code RTL (Verilog) for top level Ethernet wrappers to allow for user specific
- Technology specific transceiver wrappers for the selected device family
- Source code RTL (Verilog) for AXI4-Lite and Avalon-MM arbiters and address decoders
- Constraint files and synthesis scripts for design compilation
- Linux based APIs/tools to access core configuration and statistics registers
- Design guide(s) and user manual(s)
