10G Ultra Low Latency Ethernet FPGA IP Core Solution
The 10Gbps Ultra Low Latency Ethernet FPGA IP core solution offers a fully integrated IEEE 802.3-2015 compliant package for NIC (Network Interface Card) and Ethernet switching applications. This ultra-low latency solution is specifically targeted for demanding financial, high frequency trading and HPC applications. A fully-integrated version where the ultra-low latency 10G FPGA IP core solution is targeted for Solarflare® SFA7942Q ApplicationOnload™ Engine (AOE) is also available.
- Round Trip Latency of 52.7ns + Device Specific Transceiver Latency
- Ultra low latency MAC; Tx = 12.4ns , Rx = 15.5ns; (32-bit user interface mode with FCS Generation and checking)
- Ultra low latency 10GBase-R PCS; Tx = 12.4ns, Rx = 12.4ns;
- Technology dependent transceiver wrapper (includes clock PLLs) for Altera and/or Xilinx FPGAs
- Statistics counter block (for RMON and MIB)
- MDIO and I2C cores for optical module status and control
- Encrypted MAC and PCS RTL for simulation and synthesis
- Encrypted L2 packet generator and checker RTL for simulation and synthesis
- Source code RTL (Verilog) for top level Ethernet wrappers to allow for user specific customizations.
- Technology specific transceiver wrappers for the selected device family
- Source code RTL (Verilog) for AXI4 Lite and Avalon-MM arbiters and address decoders
- Constraint files and synthesis scripts for design compilation
- Linux based APIs/tools to access core configuration and statistics registers
- Design guide(s) and user manual(s)