Overview
The 25G/10Gbps Ultra Low Latency Ethernet FPGA IP core solution offers a fully integrated IEEE P802.3by compliant package for NIC (Network Interface Card) and Ethernet switching applications. This ultra-low latency solution specifically targeted for demanding financial, high frequency trading, HPC, and next generation 5G network applications.
Features
- Round Trip Latency of 59.6ns + Device Specific Transceiver Latency
- As shown in the figure, the 25Gbps ULL Ethernet IP solution includes:
- Ultra low latency MAC; Tx = 17.4ns , Rx = 17.4ns; (64-bit user interface mode)
- Ultra low latency 25GBase-R PCS; Tx = 12.4ns, Rx = 12.4ns; (64-bit user interface mode)
- Technology dependent transceiver wrapper (includes clock PLLs) for Altera and/or Xilinx FPGAs
- Statistics counter block (for RMON and MIB)
- MDIO and I2C cores for optical module status and control
Deliverables
- Encrypted MAC and PCS RTL for simulation and synthesis
- Encrypted L2 packet generator and checker RTL for simulation and synthesis
- Source code RTL (Verilog) for top level Ethernet wrappers to allow for user specific customizations.
- Technology specific transceiver wrappers for the selected device family
- Source code RTL (Verilog) for AXI4 Lite and Avalon-MM arbiters and address decoders
- Constraint files and synthesis scripts for design compilation
- Linux based APIs/tools to access core configuration and statistics registers
- Design guide(s) and user manual(s)
