40G Ethernet FPGA IP Core Solution

Overview

The 40Gbps Ethernet IP solution offers a highly optimized (128-bit datapath) and fully integrated IEEE802.3ba compliant package for NIC (Network Interface Card) and Ethernet switching applications.

Features

  • 40Gbps MAC core
  • 40Gbps (40GBase-R) PCS core
  • Technology dependent transceiver wrapper (includes clock PLLs) for Altera and/or Xilinx FPGAs
  • Statistics counter block (for RMON and MIB)
  • MDIO and I2C cores for optical module status and control

Deliverables

  • Ethernet wrapper design with:
    • Top level MAC and PCS wrappers (source files, Verilog) for user specific customizations
    • Compiled synthesizable binaries (Netlists) for MAC and PCS cores
    • Compiled synthesizable binaries (Netlists) for L2 packet generator and checker
    • Technology specific transceiver wrappers for the selected device family
    • Source code RTL (Verilog) for RMON and Register-File blocks
  •  UART/PCIe interface based reference design with:
    • Top level wrapper (source files, Verilog) for user specific customizations
    • Compiled synthesizable binaries (Netlists) for the I2C and MDIO cores
    • Compiled synthesizable binaries (Netlists) for the UART or PCIe host interface
  • Encrypted RTL for MAC, PCS and packet generator/checker for simulation
  • Constraint files and synthesis scripts for design compilation
  •  PCIe driver/API (source files, C) for Linux with the optional PCIe host interface
  • GUI application (Linux only) for interfacing to the reference design
  • Design guide(s) and user manuals

Product Brief

Download to get additional info

Interoperability Test Report

Download to get additional info