Firecode FEC FPGA IP Core Solution

Overview

The Forward Error Correction (FEC) FPGA IP core solution is designed to comply with the Clause 74 (FEC sublayer for 10GBASE-R, 40GBASE-R, and 100GBASE-R PHYs) of the IEEE 802.3-2008/IEEE 802.3ba-2010 specifications. The latest version, 2.2, also supports the optional FEC layer, clause 74, for the 25G Ethernet symposium as well as the IEEE 802.3by 25Gb/s specification. As shown in the figure, cyclic code (2112, 2080) FEC block lies between PCS and PMA sublayers and provides coding gain to increase the link budget and BER performance.

Features

  • Implements an FEC IP core compliant with the clause 74 of the IEEE 802.3-2008 and IEEE 802.3ba-2010 specifications.
  • Implements a 66-bit streaming interface
  • Implements a 66b/65b sync bits compression and decompression in FEC transmit and receive paths respectively.
  • Implements a (2112, 2080) shortened fire (cyclic) code encoder and decoder based on 802.3ba specified polynomial x32 + x23 + x21 + x11 + x2 +1. The 2112 bits are in the format of 32 66-bit words.
  • Implements the pseudo noise generator for scrambling the generated codeword based on the polynomial x58 + x39 + 1. The reverse is done in the FEC RX path.
  • The decoder also has an extra bit slip block to make sure the FEC decoder gets the aligned frame. Until the alignment is reached, the bit slip block continues to receive “uncorrectable signal” from the decoder. Once correct frame is determined for 4 consecutive frames, the bit slip locks the bit slip position and the decoder asserts the sync bit high.
  • Streaming design allows easy integration in PCS layers.
  • Only the decoder requires memory for error correction.
  • Implements cyclic error correcting code (2112, 2080) compliant with IEEE 802.3ba Specifications.
  • Decoder can correct single burst error of up to 11 bits with 53 40-bit words or 32 66-bit words or 2112 bits.
  • Implements block synchronization and pseudorandom noise scrambling as described in 802.3ba specifications.
  • Encoder and pseudo random noise generator is test with test cases provided in 802.3ba specification.
  • Error correction capability and block synchronization is tested on hardware with 40G PCS and MAC with more than 1,000 random scenarios.
  • Supports streaming interface.

Deliverables

  • Compiled synthesizable binaries or synthesizable source code (Verilog); depending upon license type
  • Test bench in system Verilog with random frame data and error injection
  • Behavioral Model
  • Golden test vectors from standard
  • User Documentation
  • Synthesis scripts for multi-platform FPGAs

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