5GNR LDPC
IP Core Solution

Overview

The 5G LDPC IP core implements Low-density parity-check (LDPC) codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specifications. LDPC codes are linear error correcting codes used to transmit and receive messages over noisy channels. The LDPC IP core is designed to comply with the 3GPP TS 38.212, Release 15 specifications.

Features

  • Supports per block configurable block length, code rate, base graph, and maximum number of iterations
  • Supports serial or semi-parallel input/output hard decision bits interface for LDPC encoder
  • Supports serial or semi-parallel input/output soft decision interface for LDPC encoder
  • Supports 5-bit or 6-bit LLR soft decision precision
  • Supports a maximum of 255 iterations for LDPC decoder
  • Supports early exit of decoding operation based on syndrome check after each iteration
  • Implements Low Latency decoder ensuring high throughput

Product Brief

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