GiGE/Triple-Speed Ethernet MAC FPGA IP Core Solution
The GiGE Triple-Speed Ethernet MAC FPGA IP Core Solution offers an IEEE802.3-2008 compliant solution that meets the requirements for full-duplex GiGE LAN in NIC (Network Interface Card) applications.
- GiGE / Triple-speed MAC with GMII PCS side interface and a simple FIFO based user side interface
- GMII to RGMII interface wrapper
- Statistics counter block (for RMON and MIB)
- MDIO cores for external PHY status/control
- Encrypted MAC and PCS RTL for simulation and synthesis
- Encrypted L2 packet generator and checker RTL for simulation and synthesis
- Source code RTL (Verilog) for top level Ethernet wrappers to allow for user specific customizations.
- Technology specific transceiver wrappers for the selected device family
- Source code RTL (Verilog) for AXI4 Lite and Avalon-MM arbiters and address decoders
- Constraint files and synthesis scripts for design compilation
- Linux based APIs/tools to access core configuration and statistics registers
- Design guide(s) and user manual(s)