RS-FEC (528,514)

Overview

The Reed-Solomon Forward Error Correction (RS-FEC) IP Solution implements the RS-FEC sublayer specified in IEEE 802.3by/D3.1. This high through-put design is targeted for demanding, high frequency applications and provides bypass capabilities for direct access to sub designs. The target frequency is 390.625MHz for up to 100Gbps operation.

Features

  • 100Gbps MAC core with AXI-4 Streaming or Avalon Streaming user interface
  • 100Gbps (100GBase-R) PCS core with support for CAUI-4 (-C4 option) or CAUI-10 (-C10 option)
  • Technology dependent transceiver wrapper (includes clock PLLs) for Altera and/or Xilinx FPGAs
  • Statistics counter block (for RMON and MIB)
  • MDIO and I2C cores for optical module status and control

Deliverables

  • Ethernet wrapper design with:
    • Top level MAC and PCS wrappers (source files, Verilog) for user specific customizations
    • Compiled synthesizable binaries (Netlists) for MAC and PCS cores
    • Compiled synthesizable binaries (Netlists) for L2 packet generator and checker
    • Technology specific transceiver wrappers for the selected device family
    • Source code RTL (Verilog) for RMON and Register-File blocks
  • UART/PCIe interface based reference design with:
    • Top level wrapper (source files, Verilog) for user specific customizations
    • Compiled synthesizable binaries (Netlists) for the I2C and MDIO cores
    • Compiled synthesizable binaries (Netlists) for the UART or PCIe host interface
  • Encrypted RTL for MAC, PCS and packet generator/checker for simulation
  • Constraint files and synthesis scripts for design compilation
  • PCIe driver/API (source files, C) for Linux with the optional PCIe host interface
  • GUI application (Linux only) for interfacing to the reference design
  • Design guide(s) and user manuals

Product Brief

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