100G Ethernet FPGA IP Core Solution


The 100Gbps Ethernet FPGA IP core solution offers a fully integrated IEEE802.3ba compliant package for NIC (Network Interface Card) and Ethernet switching applications.


  • 100Gbps MAC core with AXI-4 Streaming or Avalon Streaming user interface
  • 100Gbps (100GBase-R) PCS core with support for CAUI-4 (-C4 option) or CAUI-10 (-C10 option)
  • Technology dependent transceiver wrapper (includes clock PLLs) for Altera and/or Xilinx FPGAs
  • Statistics counter block (for RMON and MIB)
  • MDIO and I2C cores for optical module status and control


  • Encrypted MAC and PCS RTL for simulation and synthesis
  • Encrypted L2 packet generator and checker RTL for simulation and synthesis
  • Source code RTL (Verilog) for top level Ethernet wrappers to allow for user specific customizations.
  • Technology specific transceiver wrappers for the selected device family
  • Source code RTL (Verilog) for AXI4 Lite and Avalon-MM arbiters and address decoders
  • Constraint files and synthesis scripts for design compilation
  • Linux based APIs/tools to access core configuration and statistics registers
  • Design guide(s) and user manual(s)

Product Brief

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Interoperability Test Report

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