10G Low Latency Ethernet FPGA IP Core Solution

Overview

The 10Gbps LL Ethernet IP solution offers a fully integrated IEEE 802.3-2015 compliant package for NIC (Network Interface Card) and Ethernet switching applications. This low latency solution is specifically targeted for demanding financial, high frequency trading and HPC applications.

Features

  • Low latency MAC; Tx = 50.0ns , Rx = 70.4ns; (32-bit user interface mode)
  • Low latency 10GBase-R PCS; Tx = 77.1ns, Rx = 121.3ns; (32-bit user interface mode)
  • Technology dependent transceiver wrapper (includes clock PLLs) for Altera and/or Xilinx FPGAs
  • Statistics counter block (for RMON and MIB)
  • MDIO and I2C cores for optical module status and control

Deliverables

1. Ethernet wrapper design with:

    • Top level MAC and PCS wrappers (source files, Verilog) for user specific customizations
    • Compiled synthesizable binaries (Netlists) for MAC and PCS cores
    • Compiled synthesizable binaries (Netlists) for L2 packet generator and checker
    • Technology specific transceiver wrappers for the selected device family
    • Source code RTL (Verilog) for RMON and Register-File blocks

2. UART/PCIe interface based reference design with:

    • Top level wrapper (source files, Verilog) for user specific customizations
    • Compiled synthesizable binaries (Netlists) for the I2C and MDIO cores
    • Compiled synthesizable binaries (Netlists) for the UART or PCIe host interface

3. Encrypted RTL for MAC, PCS and packet generator/checker for simulation

4. Constraint files and synthesis scripts for design compilation

5. PCIe driver/API (source files, C) for Linux with the optional PCIe host interface

6. GUI application (Linux only) for interfacing to the reference designDesign guide(s) and user manuals

Product Brief

Download to get additional info

Competitive Analysis

Download to get additional info